View CA342005_1223922.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
CA3420
Data Sheet October 4, 2005 FN1320.9
0.5MHz, Low Supply Voltage, Low Input Current BiMOS Operational Amplifier
The CA3420 is an integrated circuit operational amplifier that combines PMOS transistors and bipolar transistors on a single monolithic chip. The CA3420 BiMOS operational amplifier features gate protected PMOS transistors in the input circuit to provide very high input impedance, very low input currents (less than 1pA). The internal bootstrapping network features a unique guardbanding technique for reducing the doubling of leakage current for every 10C increase in temperature. The CA3420 operates at total supply voltages from 2V to 20V either single or dual supply. This operational amplifier is internally phase compensated to achieve stable operation in the unity gain follower configuration. Additionally, it has access terminals for a supplementary external capacitor if additional frequency rolloff is desired. Terminals are also provided for use in applications requiring input offset voltage nulling. The use of PMOS in the input stage results in common mode input voltage capability down to 0.45V below the negative supply terminal, an important attribute for single supply application. The output stage uses a feedback OTA type amplifier that can swing essentially from rail-to-rail. The output driving current of 1.5mA (Min) is provided by using nonlinear current mirrors.
Features
* 2V Supply at 300A Supply Current * 1pA Input Current (Typ) (Essentially Constant to 85C) * Rail-to-Rail Output Swing (Drive 2mA into 1k Load) * Pin Compatible with 741 Operational Amplifiers * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* pH Probe Amplifiers * Picoammeters * Electrometer (High Z) Instruments * Portable Equipment * Inaccessible Field Equipment * Battery-Dependent Equipment (Medical and Military)
Functional Diagram
X1
Ordering Information
PART NUMBER CA3420E CA3420EZ (Note) PART MARKING CA3420E CA3420EZ TEMP. RANGE (C) -55 to 125 -55 to 125 PACKAGE 8 Ld PDIP 8 Ld PDIP* (Pb-free) PKG. DWG. # E8.3 E8.3
X1
MOS BIPOLAR + MOS BIPOLAR
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
BUFFER AMPS; BOOTSTRAPPED INPUT PROTECTION NETWORK
HIGH GAIN (50K)
OTA BUFFER (X2)
Pinout
CA3420 (PDIP) TOP VIEW
OFFSET NULL INV. INPUT NON-INV. INPUT V-
1 2 3 4
8 STROBE
+
7 V+ 6 OUTPUT 5 OFFSET NULL
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
CA3420
Absolute Maximum Ratings
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ + 8V) to (V- -0.5V) Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Output Short Circuit Duration (Note 1). . . . . . . . . . . . . . . . Indefinite
Thermal Information
Thermal Resistance (Typical, Note 2) JA (C/W) JC (C/W) PDIP Package* . . . . . . . . . . . . . . . . . . 105 N/A Maximum Junction Temperature (Plastic Package) . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300C *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 125C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Short circuit may be applied to ground or to either supply. 2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER Input Resistance Input Capacitance Output Resistance Equivalent Input Noise Voltage Short-Circuit Current To Opposite Supply Gain Bandwidth Product Slew Rate Transient Response Current from Terminal 8
Typical Values Intended Only for Design Guidance, VSUPPLY = 10V, TA = 25C SYMBOL RI CI RO eN Source Sink IOM+ IOMfT SR Rise Time Overshoot To VTo V+ tR OS I8 + I8RL = 2k, CL = 100pF f = 1kHz f = 10kHz RS = 100 TEST CONDITIONS TYP 150 4.9 300 62 38 2.6 2.4 0.5 0.5 0.7 15 20 2 UNITS T pF nV/Hz nV/Hz mA mA MHz V/s s % A mA
Electrical Specifications
For Equipment Design, At VSUPPLY = 1V, TA = 25C, Unless Otherwise Specified SYMBOL |VIO| |IIO| |II| AOL CMRR VlCR+ VlCRPSRR VOM+ VOMI+ PD VlO/T VIO/V RL = RL = 10k TEST CONDITIONS MIN 10 80 55 0.2 60 0.90 -0.85 TYP 5 0.01 1 100 100 560 65 0.5 -1.3 100 80 0.95 -0.91 350 0.7 4 MAX 10 4 5 1800 1000 650 1.1 UNITS mV pA pA kV/V dB V/V dB V V V/V dB V V A mW V/C
PARAMETER Input Offset Voltage Input Offset Current (Note 3) Input Current (Note 3) Large Signal Voltage Gain Common Mode Rejection Ratio Common Mode Input Voltage Range Power Supply Rejection Ratio Max Output Voltage Supply Current Device Dissipation Input Offset Voltage Temperature Drift NOTE:
3. The maximum limit represents the levels obtainable on high speed automatic test equipment. Typical values are obtained under laboratory conditions.
2
FN1320.9 October 4, 2005
CA3420
Electrical Specifications
For Equipment Design, at VSUPPLY = 10V, TA = 25C, Unless Otherwise Specified SYMBOL |VIO| |IIO| |II| AOL CMRR VlCR+ VlCRPower Supply Rejection Ratio Max Output Voltage Supply Current Device Dissipation Input Offset Voltage Temperature Drift NOTE: 4. The maximum limit represents the levels obtainable on high speed automatic test equipment. Typical values are obtained under laboratory conditions. PSRR VOM+ VOMI+ PD VlO/T VIO/V RL = RL = 10k TEST CONDITIONS MIN 10 80 Common Mode Rejection Ratio Common Mode Input Voltage Range 70 8.5 -10 70 9.7 -9.7 TYP 5 0.03 0.05 100 100 100 80 9.3 -10.3 32 90 9.9 -9.85 450 9 4 MAX 10 4 5 320 320 1000 14 UNITS mV pA pA kV/V dB V/V dB V V V/V dB V V A mW V/C
PARAMETER Input Offset Voltage Input Offset Current (Note 4) Input Current (Note 4) Large Signal Voltage Gain
Typical Applications
Picoammeter Circuit
The exceptionally low input current (typically 0.2pA) makes the CA3420 highly suited for use in a picoammeter circuit. With only a single 10G resistor, this circuit covers the range from 1.5pA. Higher current ranges are possible with suitable switching techniques and current scaling resistors. Input transient protection is provided by the 1M resistor in series with the input. Higher current ranges require that this resistor be reduced. The 10M resistor connected to pin 2 of the CA3420 decouples the potentially high input capacitance often associated with lower current circuits and reduces the tendency for the circuit to oscillate under these conditions.
1M 10G 10M
10pF +1.5V 2
CA3420 + 5 1
7 6 4 BATTERY RETURNS
500-0-500 A M 50pA 15pA 5pA -1.5V 1.5pA 1.5k 1.5k, 1% 1k 430, 1%
3
10k
150, 1%
11k
68 1%
High Input Resistance Voltmeter
Advantage is taken of the high input impedance of the CA3420 in a high input resistance DC voltmeter. Only two 1.5V "AA" type penlite batteries power this exceedingly high-input resistance (>1,000,000M) DC voltmeter. Full-scale deflection is 500mV, 150mV, and 15mV. Higher voltage ranges are easily added with external input voltage attenuator networks. The meter is placed in series with the gain network, thus eliminating the meter temperature coefficient error term. Supply current in the standby position with the meter undeflected is 300A. At full-scale deflection this current rises to 800A. Carbon-zinc battery life should be in excess of 1,000 hours.
FIGURE 1. PICOAMMETER CIRCUIT
+1.5V 3 22M 10M 100pF 2 + CA3420 7 6 4 BATTERY RETURNS 500-0-500 A M 500mV 1.5k 1.5k, 1% 1k 50mV -1.5V 15mV 150, 1% 430, 1%
1 5
10k
150mV
1.1k
68 1%
FIGURE 2. HIGH INPUT RESISTANCE VOLTMETER
3
FN1320.9 October 4, 2005
CA3420 Typical Performance Curves
INPUT & OUTPUT VOLTAGE EXCURSIONS FROM THE POSITIVE AND NEGATIVE SUPPLY VOLTAGE (V) OUTPUT STAGE TRANSISTOR SATURATION VOLTAGE, Q19 (mV) 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1 5 10 15 SUPPLY VOLTAGE (V) VO+ VICRVICR+ V OTA = 25C RL = 100k 10 TA = 25C V- = 0V V+ = 2V V+ = 5V V+ = 10V V+ = 20V 100
1000 0.01
0.1
1
10
LOAD (SOURCING) CURRENT (mA)
FIGURE 3. OUTPUT VOLTAGE SWING AND COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE
OUTPUT STAGE TRANSISTOR SATURATION VOLTAGE, Q17 (mV) 1000 TA = 25C V+ = 0V
FIGURE 4. OUTPUT VOLTAGE vs LOAD SOURCING CURRENT
EQUIVALENT INPUT NOISE VOLTAGE (nV/Hz)
1000 VS = 10V VS = 5V VS = 1V 100 TA = 25C
100
V- = -20V V- = -10V V- = -5V V- = -2V
10
10 0.01
0.1
1
10
1 101
102
103
104
105
106
LOAD (SINKING) CURRENT (mA)
FREQUENCY (Hz)
FIGURE 5. OUTPUT VOLTAGE vs LOAD SINKING CURRENT
FIGURE 6. INPUT NOISE VOLTAGE vs FREQUENCY
100 OPEN LOOP VOLTAGE GAIN (dB)
0 -45 -90
80
60
-135 -180
40
20
0
1
101
102
103
104
105
106
FREQUENCY (Hz)
FIGURE 7. OPEN LOOP GAIN AND PHASE SHIFT RESPONSE
4
OPEN LOOP PHASE (DEGREES)
TA = 25C VS = 5V RL = 10k CL = 0pF
FN1320.9 October 4, 2005
CA3420 Dual-In-Line Plastic Packages (PDIP)
N INDEX AREA E1 12 3 N/2 -B-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 -CA2 L A C L E
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 B B1 C D D1 E E1 e eA eB L N MIN 0.015 0.115 0.014 0.045 0.008 0.355 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.400 0.325 0.280 MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 9.01 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 10.16 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93
e
A1
eA eC
C
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
0.100 BSC 0.300 BSC 0.115 8 0.430 0.150 -
2.54 BSC 7.62 BSC 10.92 3.81 8
2.93
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 5
FN1320.9 October 4, 2005

▲Up To Search▲

Price & Availability of CA342005

	To Download CA342005 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .